The invention relates to high speed circuits for electronic systems. In particular, the invention relates to high speed one-shot circuits and their applications in heavily loaded driver circuits.
A one-shot circuit (or xe2x80x9cone-shotxe2x80x9d) is a circuit that provides an output pulse of limited duration in response to an active edge on an input signal. The active edge can be a rising or a falling edge, and the output pulse can be a high pulse or a low pulse. A one-shot that provides a high pulse is referred to herein as a xe2x80x9cone-shot highxe2x80x9d, while a one-shot that provides a low pulse is referred to as a xe2x80x9cone-shot lowxe2x80x9d.
One-shots are widely used in integrated circuits (ICs) to provide temporary control signals. For example, signals generated by one-shots are used to turn transistors on or off, latch signals into memory cells, suppress signals or actions to gain additional time to perform other actions, to synchronize signals, and so forth.
FIG. 1 shows a well known one-shot high circuit 100 that provides a high pulse on an output terminal OUT in response to a rising edge on a signal on input terminal IN. The waveforms for circuit 100 are illustrated in FIG. 1A.
One-shot 100 includes a delay line 120, which comprises inverters 101-105 coupled in series, and AND circuit 110, which comprises NAND-gate 106 and inverter 107 also coupled in series. NAND-gate 106 is driven by input terminal IN and by input terminal IN delayed by delay line 120. Inverter 107 provides output signal OUT. Delay line 120 can include any odd number of inverters, such that the output pulse has the desired width.
One-shot 100 functions as follows. As shown in FIG. 1A, initially signal IN is low and node A is high, therefore, output signal OUT is low. At time T0 input signal IN goes high. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) Both input signals to AND circuit 110 are now high, so output signal OUT goes high at time T1. The delay Td between times T0 and T1 is the delay through AND circuit 110.
Meanwhile, the high value on input terminal IN propagates through delay line 120, resulting in a low value at node A at time T2. The delay TdL between times T0 and T2 is the delay through delay line 120. The low value on node A results in a low value on output terminal OUT after an additional delay Td, at time T3.
Clearly, input signal IN cannot be allowed to go low again before node A goes low at time T2, or the width of the output high pulse will be reduced. In practice, because the delay of the delay line and the width of the output pulse can depend on factors such as temperature, operating voltage, and process variations, circuits are generally designed to wait until the one-shot output pulse is complete before returning the input signal to its initial value. In fact, typically a margin of error Tmargin is added after signal OUT goes low, before signal IN is allowed to return to a low value at time T4.
In response to the low value on signal IN, node A goes high again after another delay TdL, at time T5. Again, a margin of error Tmargin is typically added after node A goes high before signal IN is allowed to go high again. Thus, the minimum time period Tmin between high edges on input signal IN is Td+2 (TdL+Tmargin).
FIG. 2 shows a well known one-shot low circuit 200 that provides a low pulse on an output terminal OUT in response to a falling edge on a signal on input terminal IN. The waveforms for circuit 200 are illustrated in FIG. 2A.
One-shot 200 includes a delay line 220, which comprises inverters 201-205 coupled in series, and OR circuit 210, which comprises NOR-gate 206 and inverter 207 also coupled in series. NOR-gate 206 is driven by input terminal IN and by input terminal IN delayed by delay line 220. Inverter 207 provides output signal OUT. Delay line 220 can include any odd number of inverters, such that the output pulse has the desired width.
One-shot 200 functions in a fashion similar to one-shot 100 of FIG. 1. As can be seen in FIG. 2A, a falling edge on input signal IN triggers a falling edge on output signal OUT, after a delay Td (the delay through OR circuit 210). However, the subsequent rising edge on output signal OUT is triggered by a rising edge on node B, after a delay Td+TdL, where TdL is the delay through delay line 220. Thus, the width of the low output pulse is determined by the delay through delay line 220, while the minimum time period between subsequent falling edges on input signal IN is again Td+2(TdL+Tmargin).
As described above, the conventional one-shots of FIGS. 1 and 2 are widely used in control circuits. However, they are generally not applied to speed-critical circuit paths, for several reasons. Firstly, the delay between the active edge on the input signal and the onset of the output pulse (Td) can also be undesirable. Secondly, the minimum time period between subsequent active edges on the input signal (Td+2(TdL+Tmargin)) is often too long for speed-critical paths. Last but not least, the circuits of FIGS. 1 and 2 can be sensitive to process shifts. For example, a process corner that results in very fast inverters (i.e., a very short TdL) will result in a very short output pulse. In extreme cases, the output pulse width can be reduced to the point where it fails to do its job in properly controlling other circuits. At the opposite extreme, a very slow process corner can result in an extended output pulse that will adversely affect system performance.
Therefore, it is desirable to provide high-speed one-shot circuits, preferably having reduced susceptibility to process shifts. These high-speed one-shot circuits could potentially be used in applications in which one-shots have not previously been applied, for example in high-speed, heavily loaded driver circuits such as output driver circuits for ICs.
According to a first aspect of the invention, a one-shot circuit is provided that reacts quickly to changes to an input signal, thereby increasing the maximum supported frequency of the input signal.
According to one embodiment, a one-shot high generates a high output signal from an output circuit in response to a rising edge on the input signal, while the signal also travels through a delay chain towards the output circuit as in a conventional one-shot. When the delayed rising edge reaches the output circuit, the one-shot output signal goes low again. However, a falling edge on the input signal resets the one-shot without waiting for the signal to pass through the delay chain. Thus, another rising edge can be applied to the input terminal shortly after the previous falling edge.
In one embodiment, the delay chain is implemented using a chain of AND circuits, each driven by the preceding circuit in the chain and by the one-shot input signal.
According to another embodiment, a one-shot low generates a low output signal from an output circuit in response to a falling edge on the input signal, while the signal also travels through a delay chain towards the output circuit as in a conventional one-shot. When the delayed falling edge reaches the output circuit, the one-shot output signal goes high again. However, a rising edge on the input signal resets the one-shot without waiting for the signal to pass through the delay chain. Thus, another falling edge can be applied to the input terminal shortly after the previous rising edge.
In one such embodiment, the delay chain is implemented using a chain of OR circuits, each driven by the preceding circuit in the chain and by the one-shot input signal.
Some embodiments provide an additional speed advantage by implementing the output circuit as a pass gate coupled between the input terminal and the output terminal, and controlled by the output of the delay chain. A pulldown (for the one-shot high) or a pullup (for the one-shot low) is coupled to the output terminal and also controlled by the output of the delay chain, to provide an inactive value when the pulse is not being applied.
Other embodiments offer programmable capabilities. For example, some embodiments allow a user to correct for process shift by altering the effective delay of the delay chain. According to one such embodiment, a multiplexer is provided that selects one of two or more points in the delay chain, and passes the selected signal to the last delay element in the delay chain. In other embodiments, the multiplexer is inserted at other points in the delay chain, e.g., earlier in the delay chain or at the end of the delay chain.
Other programmable options can include providing a tristateable output signal, tying the output terminal to power high or ground, programming the one-shot to act as a simple delay chain, or simply bypassing the one-shot circuit to pass the input signal to the output terminal.
According to a second aspect of the invention, a driver circuit is provided that can drive heavily loaded signals at high speeds with a reduced crowbar current. In a conventional driver circuit, the output pullup and pulldown are typically turned on simultaneously for a significant period of time when the output signal changes state. Thus, current flows between ground and power high. This current is referred to herein as a crowbar current. The crowbar current increases the power consumption of the circuit. The contention between the pullup and pulldown also increases the time required for the circuit output to change state. In the driver circuit of the invention, one-shots are used to drive the pullup and pulldown, thereby minimizing the period when pullup and pulldown are both turned on. One-shots according to the first aspect of the invention are preferably used.
One such embodiment includes an inverter, a one-shot low circuit, a one-shot high circuit, a pullup, and a pulldown. The inverter is driven by a driver input signal and has an output terminal coupled to the driver output terminal. The pullup and pulldown are coupled to the driver output terminal. The one-shot low circuit is driven by the driver input signal and controls the pullup, which in one embodiment is a P-channel transistor. The one-shot high circuit is driven by the driver input signal and controls the pulldown, which in one embodiment is an N-channel transistor.
According to another embodiment, a driver circuit includes two pre-driver circuits, one controlling an output pullup and the other controlling an output pulldown. Each of the pre-driver circuits is implemented using a one-shot low and a one-shot high, as described above. This driver circuit can be made sufficiently powerful to act as an output driver circuit for an IC. In one embodiment, the IC is a programmable logic device (PLD), and programmable capabilities such as those described above are provided.